Mixed-Voltage-Tolerant I/O Buffer Design

A fully mixed-voltage-tolerant I/O buffer implemented using typical CMOS 2P4M 0.35 mum process is proposed in this paper. Unlike traditional mixed-voltage-tolerant I/O buffers, the fully mixed-voltage-tolerant I/O buffer can transmit and receive the signals with voltage levels of 5/3.3/1.8 V. By using stacked PMOS and stacked NMOS at the output stage and a level converter providing appropriate control voltages for the gates of the stacked PMOS, the gate-oxide overstress and hot-carrier degradation are avoided. Moreover, gate-tracking and floating N-well circuits are used to remove the undesirable leakage current paths. The HSPICE simulation results reveal that the gate-oxide reliability is confirmed. The maximum transmitting speed of the proposed I/O buffer is 103/120/84 Mbps for the supply voltage of I/O buffer at 5/3.3/1.8 V, respectively, given the load of 20 pF.