1.2Gbps LVDS interface

A low voltage differential signaling (LVDS) interface circuit for inter-chip communication in a DSL system has been designed, integrated and verified in 130 nm CMOS technology. Tailored for low supply voltage, the nominal transmitter differential output voltage is 330 mV with 640 mV common-mode (CM) so it is not fully compatible with the LVDS standard. To achieve high data rate performance, DC closed loop control was used in the transmitter together with wide CM input multi-stage receiver and source/load termination. 1.2 Gbps operation at 1.5 V supply was measured on fabricated test chips comprising LVDS transmitter, receiver, serial-to-parallel data framing and clocking. Power dissipation with one set of Receiver/Transmitter active and BIST has been measured to be 67.5 mW and the area of the interface is 0.45 mm².