Simulation and Analysis of Fully Depleted Strained-Si SOI MOSFET

A systematic study on the fully depleted strained-Si SOI MOSFET has been demonstrated in this paper. The strained-Si n-FET and p-FET both show significant drain current enhancement of 21% and 14.3%, and peak-Gm enhancement of 16.3% and 10%, respectively. The enhancement in n-FET is larger than that in p-FET due to more significant mobility enhancement for electron than for hole. Moreover, the relationship between threshold-voltage and Ge content is also examined. It is confirmed that threshold-voltage decreases with increasing of Ge content. Therefore, there must be a trade off in Ge content depending on device electrical characteristics.