CMOS combinational logic design for GaAs heterostructure MOSFET technology

In this paper, we evaluate the impact of GaAs MOSFET technology on the design of CMOS combinational logic. A BSIM model is developed for both GaAs pMOS and nMOS transistors based on the underlying device physics, drift-diffusion simulations, and measured data. An elementary family of logic gates are implemented using these models and a set of optimal transistor sizing ratios are established. This is achieved by adopting a delay model that minimises the average rise and fall times of the logic gates.