Integrated switchable inductors with symmetric differential layout

An integrated switchable inductor with symmetric differential layout is proposed. It can be achieved over 50% area shrinkage as compared with the traditional ones. Three testkeys with a typical switch-ON inductance of about 2.1 nH (at 1.8 GHz) were pre-designed using an electromagnetic simulator and successfully verified by tsmc’s 0.18 μm RF CMOS technology. The measured ON/OFF inductance values are of 2.1 nH / 2.7 nH, 2.1 nH / 2.4 nH and 2.0 nH / 2.2 nH; and the Q-factors are of 4.1 / 6.2, 4.6 / 6.1 and 5.1 / 6.1, respectively. The Q-factor degradation of proposed switchable inductors due to the different inner turn size effect is discussed and a simple inductor lumped-circuit model is proposed with a relatively reasonable accuracy up to 10 GHz. A VCO testkey with the integration of such switchable inductor is also demonstrated.