Characterization of latch-up in CMOS inverters in pulsed electromagnetic interference environments

Latch-up effects in cascaded CMOS inverters due to pulsed electromagnetic interference (PEMI) from high power microwave sources, is reported. The cascaded inverters were designed and fabricated consisting of two identical inverters with a width to length ratio (W/L) of 3.2 mum/1.6 mum for n MOSFETs and 9.6 mum/1.6mum for p MOSFETs. The inverters were packaged and placed in a PC board for measurements.