Technological constrains of bulk FinFET structure in comparison with SOI FinFET

In order to obtain bulk FinFET characteristics that closely match SOI FinFET characteristics, meaning DIBL below 70 mV/V @ I_D = 10^-6 A and subthreshold swing below 100 mV/dec @ V_DS = 1.2 V, source/drain junction depths must be aligned to the bottom of the gate and the fin width of the bulk FinFET must be 20 nm at most assuming the gate length of 50 nm. Bulk FinFET characteristics can be improved by reducing S/D junction depth with respect to the bottom of the gate (e.g. Deltax_j = -10 nm), which can be easily accomplished in fabrication.