Rapid Circuit-based Optimization of Low Operational Power CMOS Devices

We demonstrate: (i) a silicon-calibrated, low computational complexity Verilog-A MOS model coupled to rapid library generation and characterization tool set within a commercial-grade design flow, (ii) the use of this design flow for the evaluation of TCAD-based transistors in high complexity circuits with iteration times of less than three hours, (iii) the design of 16-bit multiplier circuits with low operational (static + dynamic) power CMOS devices with power savings of 84% and 76% at 25degC and 60degC, respectively, compared to an unmodified 70 nm gate length CMOS process.