An efficient programmable engine for interpolation of multi-standard video coding

This paper presents an efficient programmable engine that supports diverse interpolation algorithm in different video coding standards, such as H.264/AVC, and the Chinese national standard, AVS. It is a VLIW(very long instruction word) and SIMD(single instruction multiple data) hybrid architecture which could issue four ALU operations and one memory reference or a branch operation in every clock cycle, and execute four different data streams in a single instruction. An 8-bank 2-D on-chip memory is proposed to improve the parallelism of memory accessing. The design is implemented with Verilog-HDL, and synthesized with synopsys tools using 0.18 um Standard Cell Library. The total area is about 3.80 x 4.31 mm
²
, and the frequency can achieve 179.5 MHz.