Design and implementation of twin transport stream demultiplexor in HDTV decoder

A new architecture for transport stream demultiplexer (TS Demux) in high definition television (HDTV) decoder is presented in this paper, which is able to demultiplex two TS inputs synchronously. We have pursued a hardware-based design that controlled by the software to yield high performance in the least silicon area. The key parts of the architecture, including PID filter, section filter and Memory Control Unit (MCU), are shared by the two TS inputs in terms of a time slice. Owing to the elaborate shared mechanism, our design is efficient to support more tremendous functions with less resource compared to the current scheme.