Fractional-N phase locked loop design and applications

This paper presents fractional-N sigma-delta phase locked loop (PLL) applications and design. Applications focus primarily on wireless communication and clock synthesizers. Fractional-N PLL architectures are described in detail. The performance of multi-stage noise shaping (MASH) and single-loop sigma-delta modulators is compared. Constraints on PLL loop bandwidth while using sigma-delta modulators is discussed. The causes of fractional spurs and spur reduction techniques are demonstrated.