Low leakage dynamic circuits with dual threshold voltages and dual gate oxide thickness

In this paper, a low leakage circuit technique is proposed for simultaneously reducing the subthreshold and gate oxide leakage power in domino logic circuits. NMOS sleep transistors and dual threshold voltages, dual gate oxide thickness CMOS technologies are utilized to place an idle domino circuit into a low leakage state. The proposed circuit technique lowers the total leakage power by up to 65.7% at a temperature of 110°C and 94.1% at the room temperature as compared to the standard dual threshold voltage domino logic circuits. Similarly, a 12.3% to 61.5% reduction in total leakage power is observed as compare to a previously published sleep switch scheme in a 45nm CMOS technology.