A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop

A 4.2 GHz integer-N PLL frequency synthesizer for WLANs is described. An analog split tuned LC-VCO is controlled by coarse and fine loops to achieve both a large frequency tuning range and a small VCO gain. An averaging varactor is employed to reduce the amplitude sensitivity of the varactor, thereby reducing the AM-to-FM noise conversion. A new adaptively tuned switched capacitor integrator is used in the coarse loop for a fast lock time. The prototype test chip in a 0.13-μm CMOS process has a measured phase noise of -110dBc/Hz at 1MHz offset, and a settling time of 50 μs.