Analytical expression for signal propagation delay of off-chip interconnection for SIP application

A new analytical expression is propossed for the calculation of the delay time of off-chip pin-to-pin interconnection. This includes all the line and the load parameters for CMOS based circuits. The classical on-chip analytical formulations available in the literature have been reviewed. Spice simulations are applied to compare the accuracy of the proposed expressions. Measurement results have been used for the determination of the accuracy of the spice line model.