Process and design optimization of a protection scheme based on NMOSFETs with ESD implant in 65nm and 45nm CMOS technologies

Process and design optimization of NMOSFETs with ESD implant is presented. A 2 V reduction in trigger voltage, a 30% higher failure current, 50% reduction in on-resistance is achieved with a 13X increase in leakage current for a 2.5 V NMOSFET. Self-protected NMOSFETs with ESD implant enables 40% or larger decrease in NMOSFET area for a non-mixed voltage and mixed voltage I/O.