A Proposal on an Optimized Device Structure With Experimental Studies on Recent Devices for the DRAM Cell Transistor

We have experimentally analyzed the leakage mechanism and device degradations caused by the Fowler–Nordheim (F–N) and hot carrier stresses for the recently developed dynamic random-access memory cell transistors with deeply recessed channels. We have identified the important differences in the leakage mechanism between saddle fin (S-Fin) and recess channel array transistor (RCAT). These devices have their own respective structural benefits with regard to leakage current. Therefore, we suggest guidelines with respect to the optimal device structures such that they have the advantages of both S-Fin and RCAT structures. With these guidelines, we propose a new recess-FinFET structure that can be realized by feasible manufacturing process steps. The structure has the side-gate form only in the bottom channel region. This enhances the characteristics of the threshold voltage ($V_{\rm TH}$), ON/OFF currents, and the retention time distributions compared with the S-Fin structure introduced recently.