Implementation of Static and Semi-Static Versions of a Bit-Wise Pipelined Dual-Rail NCL 2S Complement Multiplier

This paper focuses on implementing a 2^s complement 8×8 dual-rail bit-wise pipelined multiplier using the asynchronous NULL Convention Logic (NCL) paradigm. The design utilizes a Wallace tree for partial product summation, and is implemented and simulated in VHDL, the transistor level, and the physical level, using a 1.8V 0.18μm TSMC CMOS process. The multiplier is realized using both static and semi-static versions of the NCL gates; and these two implementations are compared in terms of area, power, and speed.