A 16-Port Data Cache for Chip Multi-Processor Architecture

With the development of the modern architecture and chip integration technology, parallel process technologies have become the mainstream. The increasingly large gap between processor and memory speed has made the design of high bandwidth and large scale cache a key part in high performance microprocessor. In this paper, we describe the design of a 16-port data cache, which is 8-way associative using pseudo-LRU replacement policy. The interleaved storage and cross-switch interconnection techniques enable the cache can response for up to 16 concurrent access requests.