FDTD Analysis of Multichip Vertical Interconnects

In this paper we present computer FDTD simulations for multichip interconnects between CPW transmission lines in two different layers and a CPW chip (CPW-CPW-CPW) using metallic, spherical bumps. We show that the main influence on the performance of the entire CPW-CPW-CPW structure has the first level of interconnection, where via holes are used. A reduction in return loss can be achieved by using small bump dimensions in the first level of the assembly.