Time Discrete Voltage Sensing and Iterative Programming Control for a 4F2Multilevel CBRAM

Multilevel read/write circuits developed for a 90nm, 4F², 1T1CBJ (1-T̲ransistor/1-C̲onductive B̲ridging J̲unction) 4Mb CBRAM core are described for the first time. The design uses an on-pitch time-discrete voltage sensing scheme and employs a bitline (BL) charge balancing reference as well as a self-timed iterative program concept. Random read cycle times ≈0.7μs and random write cycle times 𢒁.35μs are achieved.