The Dependence of Latch-Up Sensitivity on Layout Features in CMOS Integrated Circuits

The separated source-to-substrate/well contact diffusion layout commonly used in CMOS IC design has been identified as a primary cause for latch-up sensivity in bulk CMOS devices. FXR testing as well as electrical characterization of latch-up has been conducted on test structures which separately contain either separated or butted source-to-substrate/well layout. SPICE simulations using device parameters derived from the PISCES code have been performed to confirm the experimental results. Reduced substrate resistances and field degraded vertical transistor gains seem to be the reasons for high latch-up immunity of the butted layout. Latch-up free bulk CMOS ICs can be fabricated using the butted layout design rules, which can eliminate costly hardness assurance measures such as 100 % screening.