Design of CMOS/SOS Circuits for Space Applications

Requirements of integrated circuits for space applications are high speed, small size and great reliability. The CMOS/SOS process technology inherently fulfills these requirements. Recently discovered problems of reliability are soft errors or "bit-flips" induced by galactic cosmic rays or terrestrial ∝-particles. This paper discusses CMOS/SOS circuit design which minimizes these errors. A design example is given for D flip-flop as a typical storage element, and a comparison is made between 4 μm, 2 μm, and 1 μm channel lengths. Results obtained for short channel lengths indicate that the design of VLSI circuits for space applications with CMOS/SOS technology is feasible and realistic.