High Level Fixed Point VLSI Design with Automated Clock Gating

Here we present a high level VLSI design platform, which supports the use of fixed point operations and automated clock gating of registers. This platform has been implemented by extending the CoDeL design suite. CoDeL allows hardware description at the algorithm level, and thus dramatically reduces design time. Also, it automatically inserts clock gating at the behavioral level to reduce dynamic power dissipation in the resulting architecture. This is, to our knowledge, the first hardware design environment that allows an algorithmic description of a component and yet produces a power aware design. We use the DSPstone benchmark to thoroughly evaluate this fixed point design platform for the design of power efficient DSP architectures. We find that, compared to a modern DSP, the CoDeL platform produces designs with somewhat slower run times but dramatically lower power dissipation. Next we use power analysis to compare the effectiveness of CoDeL's automated clock gating as compared to automated clock gating using synopsys tools. A simulation based power analysis shows that CoDeL's clock gating provides 16% more power savings than Synopsys' automated clock gating alone.