Optimization of Moore FSM on FPGA

A new method of Moore FSM circuit optimization is proposed, which is based on generation of both codes of the states and codes of the classes of pseudoequivalent states of FSM. The presented method permits to encode the states of FSM in such manner that some microoperations can be implemented using single LUT element. Other microoperations should be implemented using dedicated memory blocks. Minimization of the system of excitation functions is reached thanks to separate source of the codes of the classes of pseudoequivalent states. Such approach allows minimizing hardware amount in the circuit of FSM. The conditions for such optimization are shown. An example of proposed method's application is given.