Clocking a WTA Network Under Capacitive Coupling

This paper briefly reports our recent results on timing analysis of (W)inner (T)ake (A)ll network of Hopfleld type. The mutual capacitances (technologically unavoidable for the ever decreasing chips) between amplifier inputs are considered. By handling the differential equations describing the network we give explicit formulae for time intervals of processing and resetting. They are tools for the early stages of analog processors design.