Multi-phase Clock Scan Technique for Low Test Power

Power dissipation during testing is becoming a primary concern. In this paper, a novel DFT (design for testability) technique named MPC-SCAN (Multi-phase clock scan) is presented,which significantly reduces the power dissipation during testing. MPC-SCAN technique based on multi-phase clock controlling multiple scan chains reduces SA (switch activity) and avoids simultaneous shifting operation. Compared with exiting low power scan testing techniques, MPC-SCAN technique keeps the average and peak power dissipation limit, and maintains the same fault coverage. Moreover, little DFT hardware is required. Theoretical analysis and experiment on ISCAS'89 benchmark circuits conformably show that the average and peak power dissipation are reduced by 60% and 40% respectively during testing.