A 10 Gb/s Low Swing Receiver for Power Optimization by Accelerated Bit Error Rate Testing

An improved low-swing current mode differential receiver is presented that was simulated to work at up to 10 Gb/s over 100 mm microstrip lines in FR-4 using 2 mW transmitter power and 1.2 mW receiver power. The proposed receiver architecture decouples the current to voltage conversion and the transmission line termination. It can accept lower swing signals than architectures such as CML or LVDS while maintaining low receiver power consumption. With this receiver we propose a methodology for optimizing transmitter power based on accelerated BER measurement using signal attenuation. This link was implemented using the 0.35 μm AMS SiGe process. Experimental results are shown for the link running at 2.5 Gb/s over 100 mm FR-4 microstrip lines with transmitter currents as low as 200 μA. These results also validate the accelerated BER measurement methodology for optimizing transmitter power.