Digital Channelized Wide Band Receiver Implemented with a Systolic Array of Multi-Rate FIR Filters

A new Systolic Array Digital Channelized Wide Band Receiver (DCWBR) Architecture is presented, which eliminates the requirement for De-Multiplexing and FFT Subsystems associated with a conventional DCWBR. The regular systolic array structure of pipelined multi-rate FIR filters in the new architecture presents an opportunity for increased clock frequencies and wider band widths compared to the conventional architecture. A Parallel Systolic Array DCWBR architecture is also presented, which facilitates increased resolution and improved signal arbitration. A FIR filter element of the Systolic Array has been implemented in 0.13um CMOS technology for estimating hardware and power requirements for the new DCWBR architecture.