Multilayer Coplanar Waveguide Transmission Lines Compatible with Standard Digital Silicon Technologies

On-chip transmission lines in silicon technologies suffer from the low-resistivity substrate and geometry limitations imposed by layout and metal density design rules. In this paper, we demonstrate that multilayer coplanar waveguide (MCPW) transmission lines can be utilized to overcome both problems by taking advantage of multiple metal layers available. We studied the effects of ground spacing on MCPW characteristics using electromagnetic simulations, based on process parameters from a 0.18 μm standard digital CMOS technology with 0.01 Ω-cm P+ substrate. Simulation results show that by adjusting the ground spacing, we can control the characteristics impedance, effective dielectric constant, and attenuation of MCPW lines. A test chip was designed and fabricated with MCPW, regular CPW, and microstrip lines. Measurement results verified the analysis and simulation results.