A Parallel-In Serial-Out Multiplier Using Redundant Representation for A Class of Finite Fields

A new parallel-in serial-out finite field multiplier using redundant representation for a class of fields is proposed. It has been shown that the proposed architecture has significantly lower complexity in comparison to the previously proposed architectures using the same representation. The new multiplier can be implemented in a hybrid fashion or at digit-level, which provides the designer with considerable amount of area-speed trade-offs. FPGA implementation of the proposed multiplier is also presented and compared with FPGA realization of a previously proposed multiplier.