Testing Based SoC/VLSI IP Identification and Protection Platform

In this paper, the authors propose a novel testing based SoC/VLSI intellectual property (IP) identification and protection platform in SoC/VLSI design. The principles are established for development of a new IP identification, protection procedures and digital rights management system that depends on current IP-based design flow. This platform can successfully survive synthesis, placement, and routing and identify the IP core at various design levels. The proposed method has the potential to solve the digital rights management problem in SoC/VLSI design.