Application of Genetic Algorithms for Run-Time Reconfiguration Using Flexible Bus-Macros

This paper presents updated results for experiments published in a previous conference, namely RoEduNet 2006. The purpose is to present a method of performing the task of dynamic temporal placement for run-time reconfiguration (RTR), which requires that hardware resources be allocated for specific timeslots on an FPGA. The work presents the use of genetic algorithms as the method to place pre-wired logic circuits onto the FPGA, in order to produce a non-deterministic solution for an acceptable placement. In addition, this paper will discuss the elimination of unusable placements.