Non-linearity in high gain CMOS buffer amplifiers for CCD processor applications

The linearity of CMOS buffer amplifiers is discussed. It is shown that enhancing the amplifier gain to reduce non-linearity presents limitations due to small signal gain mismatches between the two amplifier inputs. An amplifier structure and associated design precautions are proposed to overcome these limitations to some extent. As a result, a fully differential buffer used in a 12 bit 10MSamples/s video chain has been successfully designed to achieve 16 bits linearity in a low-voltage CMOS 0.35μm process.