Design of a Low Jitter Multi-Phase Realigned PLL in submicronic CMOS technology

This paper presents a novel PLL and VCO concept based on the multi-phase direct realignment. A multiphase realigned VCO and PLL operating in the 80-240MHz frequency range have been realized in 0.18μm standard CMOS process, with a 1.8V power supply voltage. A comparison between realigned and not realigned PLLs showed a jitter improvement by a factor 2 at 240MHz without increasing the power consumption, which is 2.4mW at 240MHz.