Efficient Evaluation of Substrate Warpage by Finite Element Method and Factorial Design Analysis

Warpage of flip chip package is mainly dominated by the substrate stack-up. Mismatch by coefficient of thermal expansion (CTE) and Young's modulus (E) in package materials should be responsible to this phenomenon. Also, glass transition temperature of polymeric materials such as solder mask and dielectric dominate the warping direction. In general, the substrate is modeled as a bulk material composed of anisotropic material properties, which overlooks detail may influencing mechanical behaviors. Within this study, a four-layer 21x2 lmm organic substrate is cited as an instance. This presentation will demonstrate the mechanical behavior, i.e. warpage, by ANSYSreg in two manners, the conventional heavy resource-demanding solid element and reduced layered element. The results will manifest the efficiency of layered element in modeling such a lamination structure. An in-situ, full field, and high precision optical metrology for measuring the out-of-plane displacement is conducted for correlation between simulation and experiment. The flip-chip substrate warpage under various temperature stages is captured by shadow moire. The simulation results are in excellent agreement with experiment. Base on the above discussion, we will show how to perform parametric study to provide a design reference by a scientific and statistic way. Therefore, analysis of variance (ANOVA) is adopted. Two effects of eight stack-up layer thicknesses and four copper-layer coverage are selected for 2 level factorial designs and result in 28 and 24 simulation runs, respectively. Through the statistical analysis, thickness of dielectric layers is the major factor which has dramatic effect on the warpage as temperature elevation, while coverage of copper contributes less significantly.