Chip Scale Package Design for Thermal Performance in Mobile Handsets

In today's mobile handset market the trend is to provide high performance, low cost components with integration of functionality and small form factor. With decreasing package size and increased IC functionality, thermal performance of the package becomes a concern even for components with moderate power consumption. Limited by size and cost constraints, it is a challenge for cellular phone manufacturers and IC package designers to find a way to dissipate heat without employing external cooling methods such as fans and heat sinks. There are many variables that affect package thermal performance: die size, package substrate construction, via density, and solder ball density / pattern. The challenge of package thermal design is to optimize the above parameters to achieve the best thermal solution, while also meeting system electrical, mechanical and cost requirements. This study provides insight into which package design factors will give the greatest return on thermal performance while still meeting system constraints. The focus will be on a relatively simple but widely used wirebond package we refer to as a chip scale package (CSP), with 2-metal layers and 0.5 mm solder ball pitch, in an environment with no forced convection or heat sinks. A 14times14 mm body size version was selected for analysis and is representative of current 3G baseband processor products. For a given package size, simulation results show that die size and solder ball I/O pattern have the most impact on package thermal performance. Increasing silicon area is rarely a viable option, so more time is spent investigating the impact of solder ball distribution. The thermal performance improvement from other design parameters will be analyzed but will be shown to be less of a factor.