Effect of Power and Ground Co-Reference to Performance of Memory Interface I/Os in FPGA and Structural ASIC Device Packages

In this paper, we present a summary of FPGA package development with focus on PDN and I/O co-design for optimal performance. Extensive simulation and characterization study are performed to address the effect of power and ground co-reference to memory interface I/O performance in large scale FPGA and structural ASIC devices.