A Single-Cycle-Access 128-Entry Fully Associative TLB for Multi-Core Multi-Threaded Server-on-a-Chip

A single-cycle-access, 128-entry fully-associative multi-context TLB was designed for the Niagara2 SPARCtrade processor in 65nm triple-V, 11M 1.1V CMOS. The circuit includes a dual-storage CAM cell, a modified dual matchline, an 8T 1-read/1-write based RAM, 4-way comparators for cache hit, a priority encoder, a multi-match detect, and data parity