A 62μA Interface ASIC for a Capacitive 3-Axis Micro-Accelerometer

An interface ASIC for a capacitive 3-axis micro-accelerometer is implemented in a 0.13μm CMOS process. Die area and power dissipation are reduced by using time-multiplexed sampling and duty cycles down to 0.3%. The chip with 0.51 mm² active area draws 62μA from a 1.8V supply while sampling 4 proof masses, each at 1 kS/s. With a plusmn4g capacitive 3-axis accelerometer, the measured noise in the x, y and z directions is 460μg/radicHz, 550(μg/radicHz and 550μg/radicHz, respectively.