FPGA Based Design of CAVLC and Exp-Golomb Coders for H.264/AVC Baseline Entropy Coding

This paper presents the design of a hardware architecture for the entropy coder of H.264/AVC video compression standard, considering the baseline profile. The baseline entropy coder is composed of two main blocks: Exp-Golomb coder and CAVLC coder. This paper presents the architectural design of these two blocks. These architectures were described in VHDL and synthesized to an Altera Stratix-II FPGA. From the synthesis results it was possible to verify that the Exp-Golomb and CAVLC coders reached a throughput of 15.9 million of samples per second for the Exp-Golomb coder and of 103.8 million of samples per second for CAVLC coder. The H.264/AVC baseline entropy coder is being designed through the integration of these two coders and preliminary results indicate that this solution will be able to process HDTV frames in real time.