Optimization of HW/SW Co-Design: Relevance to Configurable Processor and FPGA Technology

This paper presents a methodology for optimization of HW/SW co-design based on emerging configurable processor and FPGA technologies. This methodology is illustrated by the optimization of a discrete cosine transform (DCT) for image compression based on Tensilica's Xtensa LX core and Xilinx Virtex-II Pro device. The various optimization processes of a 2-D DCT transform, including adding different processor instruction sets onto the base processor to speedup software execution, are described. The results show a 26.76 times speed increase by adding a 4-way SIMD (single instruction multiple data) instruction with moderate hardware cost for a simple 2-D DCT implementation. The optimized 4-way SIMD processor is implemented on the FPGA board to verify the design, and shows a further significant speedup for on-board calculation compared to instruction-set simulation results. The HW vs. SW optimization strategy, speed and HW cost trade-offs, etc. are presented.