Integrating Nano-logic into an Undergraduate Logic Design Course

The goal of this work is to motivate our students and enhance their ability to address newer logic blocks namely majority gates in the existing framework. We use a K-map based methodology to introduce a few novel nano-logic design concepts for the undergraduate logic design class. We want them to possess knowledge about a few fundamental abstracted logical behaviors of future nano-devices and their functionality which in turn would motivate them to further investigate these non-CMOS emerging devices, logics and architectures. This would augment critical thinking of the students where they apply the learnt knowledge to a novel/unfamiliar situation. We intend to augment the existing standard EE and CS courses by inserting K-map based knowledge modules on nano-logic structure for stimulating their interest without significant diversion from the course framework. Experiments with our students show that all the students were able to grasp the basic concept of majority logic synthesis and almost 63% of them had a deeper understanding of the synthesis algorithm demonstrated to them.