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Magnetic Shadow RAM | IEEE Conference Publication | IEEE Xplore

Magnetic Shadow RAM


Abstract:

We propose a new shadow RAM circuit, utilizing magnetic tunnel junctions and an independent-double-gate CMOS technology. A shadow RAM combines a conventional static RAM c...Show More

Abstract:

We propose a new shadow RAM circuit, utilizing magnetic tunnel junctions and an independent-double-gate CMOS technology. A shadow RAM combines a conventional static RAM circuit with a non-volatile "shadow", and provides a means to quickly transfer data between them. Non-volatile magnetic storage offers several advantages over current technology for this application, with unlimited write endurance, very fast write time, low power consumption, and improved radiation tolerance. A novel circuit allows the shadow storage to be incorporated into a RAM cell using independent-double- gate transistors. The physical layout of the shadow RAM is unlike bulk MRAM, making it possible to embed the shadow RAM elements into computational logic without the X-Y grid decoding of the cell address. Accordingly, the micromagnetic structures have been optimized for writing with a new "one- wire" technique. We discuss proposed circuits and present circuit simulation results.
Date of Conference: 05-08 November 2006
Date Added to IEEE Xplore: 11 June 2007
Print ISBN:0-7803-9738-X
Conference Location: San Mateo, CA, USA

References

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