Experimental and Numerical Assessment of Board-Level Temperature Cycling Performance for Eutectic and Pb-free windows-Chip-Scale-Package (wCSP)

This paper examines the board-level solder joint reliability of UTAC's windows-chip-scale-package (wCSP) under temperature cycling (TC) condition, both experimentally and numerically. Five legs of wCSP test vehicles were assembled with different solder ball sizes, mold compound materials and solder materials, i.e., eutectic Pb-Sn and Sn₃Ag_0.5Cu. Those assemblies were subject to TC condition using UTAC internal TC chamber and data collection system. TC condition was specified using the widely used industry standard, which is -40degC-125degC with 15mins ramp/dwell. For the numerical study, Darveaux's approach, which uses Anand's viscoplasticity constitutive model plus fracture mechanics based fatigue model, was used for legs with eutectic 62Sn36Pb2Ag solders; while for Pb-free legs, various publicly available Pb-free constitutive and fatigue models were applied to evaluate their prediction capability