Arbitrary Duty Cycle Synchronous Mirror Delay Circuits Design

An arbitrary duty cycle synchronous mirror delay (SMD) circuit is proposed in this paper. The conventional SMD can be locked in 2 clock cycles, but it just can accept only the narrow pulse clock signal, which will greatly restrict the application of the circuits. The modified TSPC DFF is used in the proposed SMD circuit to detect clock edge. Therefore, the proposed SMD circuit not only can be locked in 2 clock cycle time but also can accept arbitrary duty cycle clocks. Moreover, it can detect a small dead zone and makes the new circuit has better jitter performance and lower static phase error. An experiment chip was fabricated in 0.18 mum CMOS process. With a 1.8 V supply voltage, the measure results show that the proposed circuits can be operated from 450 MHz to 750 MHz. When the input clock frequency is 750 MHz, the measured power dissipation was 9 mW. In addition, the peak-to-peak and rms jitters were 24 ps and 2.94 ps, respectively.