High Speed Lossless Data Compression Architecture

This paper presents a novel architecture for hardware implementation of LZ1 lossless data compression algorithm. The architecture is scalable depending upon the requirements of parallel comparisons. Several instances of the design are synthesized on an FPGA for 1 Gbits/sec and higher data rates. With the increase in network traffic, large scale digital data storage/retrieval and the requirement for preserving communication channel bandwidth, data compression is receiving enormous attention. For real time applications, hardware implementation of data compression algorithms seems imperative and the only viable solution