Efficient FPGA Implementation of Spread Spectrum Transceiver

This paper proposes an improved scheme of a spread spectrum transceiver based on FPGA, which is capable of meeting wide application requirements. In order to improve the efficiency, two critical modules are refined, one is a modified matched filter, and the other one is an improved digital carrier recovery loop. Compared with the typical matched filter scheme, the modified one can save about 31.48% of logic elements. The improved carrier recovery loop is implemented by all digital methods. It can not only be integrated into one chip without any analog section, but also consume low thermal power. Besides, in this paper, a brand-new scheme of spread spectrum communication system based on SOPC is introduced, which adopts the ALTERA Nios II embedded soft cores as the center control processor.