Novel Optimization Criteria for Loop Filter Design of Type II PLLs

The dynamics of phase locked loops (PLLs) are heavily influenced by the right choice of the loop filter parameters. A new approach for determining these parameters to meet the specification of telecommunications standards optimally is presented in this paper. The most common optimization criterium is to minimize the integral error over time of the step response. In a telecommunications system, it is more important to keep the instantaneous frequency error within a specified tolerance bandwidth around a desired frequency. When the power amplifier is integrated with the transceiver circuitry, specifications are even harder to meet. For this reason, an optimization method has been developed that features short settling times with inherent stability for any chosen loop bandwidth