5G-3 A Low-Noise Front-End Circuit for 2D cMUT Arrays

cMUT technology enables 2D array design with front-end electronic integration through flip-chip bonding or cMUT-on-CMOS process. The size of a 2D array element is constrained in both dimensions due to the aperture sampling criteria, and therefore should be less than or equal to the half of the wavelength in both dimensions. Considering large parasitic capacitances introduced by the interconnections, such small transducer elements necessitate integrated low noise front-ends for achieving acceptable pulse-echo SNR and image quality. We present a noise optimized CMOS front-end integrated circuit for 2D cMUT arrays. The circuit is designed using the 0.35 mum 50 V CMOS technology. A high voltage pulser circuit with optimized transistor dimensions provides a 75 nsec unipolar pulse of 40 V amplitude to drive the array element, while keeping the output parasitic capacitance at a minimal level. A simple NMOS switch is used for isolating the receive preamplifier. Two different amplifier topologies are tested for the output stage: a differential input current amplifier and a low-noise operational amplifier with PMOS inputs used in a transimpedance configuration. We performed complete analysis of the designed circuit using Cadence simulation tools. The results show that the noise figure of the overall circuit is less than 5 dB, yielding a noise floor of 100 muV for a 3 MHz transducer with 100% fractional bandwidth and 130 kOmega output impedance. The circuit is capable of driving a 5 pF load with unity gain. The overall layout size of the circuit is 160 times 185 mum
²
, making the designed circuit suitable for integration to 3-5 MHz cMUT elements through flip-chip bonding or cMUT-on-CMOS process