Unified Signed-Digit Number Adder for RSA and ECC Public-key Cryptosystems

RSA and ECC are currently the most widely used public key cryptosystems. The computation of RSA and ECC is based on GF(P) and GF(2p) fields respectively, and composed mainly of addition and XOR operations. An addition operation requires more computation time compared to a XOR operation. This paper proposes a new method to realize a unified architecture for both RSA and ECC public key cryptosystems using a Signed-Digit (SD) number system so that the carry propagation in the RSA computation can be avoided. Hence, the critical path for the computation of RSA and ECC with the same key length can be shortened compared to other methods using a full adder implementation. Simulation results show that for our proposed architecture the overall speed (the maximum frequency using a key length of 1024 for RSA and a key length of 160 for ECC) can be increased by approximately 28% compared to existing designs with an area of 4355 CLBs when implemented on an FPGA.